Requisition # G1906215
Job Title Crossbar Interconnect Methodology and Physical Design Flow Engineer
Post Date 10/03/2012
Division Qualcomm Incorporated
Job Area Engineering - Hardware
Location California - San Diego
California - Santa Clara
Texas - Austin
Job Function Qualcomm Communications Technologies, a.k.a. QCT - , is the world leader in wireless ICs powering the majority of 3G & 4G devices, is the largest fabless semiconductor in the world, and is consistently ranked near the top of Fortune's list of "100 Best Companies to Work For." Our Digital ASIC design team delivers cutting edge hardware and software products across every established wireless standard/protocol. We are looking for candidates for the Crossbar Interconnect Design team (multiple openings). The Crossbar team will focus on circuit design, layout, characterization, flow automation and physical design of high-speed and low-power crossbar interconnect fabrics and data path elements.
Responsibilities - Responsible for working with logic/architecture team to gather specifications.
- Design and analysis of high-speed crossbar interconnect and data path IPs.
- Responsible for data path sub-system definition.
- Create semi-custom design flows for hard macro and soft macro IP.
- Work with physical / backend design team for IP integration.
- Taking crossbar interconnect switches from start to finish including PTSI/SPICE closure and SDF delay simulations.
- Manage and support IP releases to chip team.
Skills/Experience - At least 3-5 years of industry experience in the area of high-speed, custom IP backend / physical design flows, PnR.
- Experience in setting up PD flows for custom data path elements, including relative placement/soft macro flows.
- Experience in PTSI, timing closure, constraints, power planning, and CTS is a must.
- Strong background in automation using Perl/Tcl/Shell scripting and UNIX administration.
- Familiarity with standard cell characterization flow.
- Good communication and teamwork skills.
Education Requirements Bachelor's required, Master's or Doctorate preferred.
Keywords interconnect switch, network-on-chip