Job Description: ASIC Engineer
-ASIC design or verification experience is required
- networking industry experience is required
- good knowledge of verilog needed
- knowledge of verilog, c++, scripting a plus
- Min 5 years of experience in networking design
- Min 5 years of experience in verilog coding and synthesis/timing
- Looking for 5-10 years of experience
Looking for smart motivated, team oriented problem solver, capable of handling legacy code and new code
